收藏本站
CS5461A
iCPU
K[3:0]
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising-edge logic
Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. A value of “0000” will set K to 16 (not zero). K = 1 at reset.
6.2 Current and Voltage DC Offset Register ( I DCoff ,V DCoff )
Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
MSB
LSB
-(2 0 )
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
.....
2 -17
2 -18
2 -19
2 -20
2 -21
2 -22
2 -23
Default = 0x000000
The DC Offset registers (I DCoff ,V DCoff ) are initialized to 0.0 on reset. When DC Offset calibration is performed, the
register is updated with the DC offset measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system offset compensation. The value is repre-
sented in two's complement notation and in the range of -1.0 ? I DCoff , V DCoff ? 1.0, with the binary point to the
right of the MSB.
6.3 Current and Voltage Gain Register ( I gn ,V gn )
Address: 2 (Current Gain); 4 (Voltage Gain)
MSB
LSB
2 1
2 0
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
.....
2 -16
2 -17
2 -18
2 -19
2 -20
2 -21
2 -22
Default = 0x400000 = 1.000
The gain registers (I gn ,V gn ) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,
the register is updated with the gain measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system gain compensation. The value is in the
range 0.0 ? I gn ,V gn < 3.9999, with the binary point to the right of the second MSB.
6.4 Cycle Count Register
Address: 5
MSB
LSB
2 23
2 22
2 21
2 20
2 19
2 18
2 17
2 16
.....
2 6
2 5
2 4
2 3
2 2
2 1
2 0
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle . During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024 ? N). A one second computational cycle period occurs when
MCLK = 4.096 MHz, K = 1, and N = 4000.
DS661F3
27
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
CDB5466U BOARD EVAL & SOFTWARE CS5466 ADC
CDB5467U BOARD EVAL FOR CS5467 ADC
CDB5560-2 DEV BOARD FOR CS5560 W/SE INPUT
CDB5571-2 DEV BOARD FOR CS5571 W/SE INPUT
CDB8422 BOARD EVAL FOR CS8422 RCVR
CDB8952T BOARD EVAL FOR CS8952
CDCE906-706PERFEVM EVAL MOD PERFORMANCE CDCE906/706
CEVAL-033 BOARD EVAL FOR CVCO33 .3"X.3"
相关代理商/技术参数
CDB5461AU-Z 制造商:Cirrus Logic 功能描述:PB-FREEEVAL BOARD FOR CS5461 WITH USB - Bulk
CDB5462 制造商:Cirrus Logic 功能描述:EVAL BOARD FOR CS5462 - Bulk
CDB5463U 功能描述:数据转换 IC 开发工具 Eval Bd Sngl-Phase Pow/Energy RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V
CDB5463U-Z 功能描述:EVAL BOARD USB FOR CS5463 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件
CDB5464U 功能描述:数据转换 IC 开发工具 Eval Bd 3-Ch Sngl-Phs Pow/Energy RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V
CDB5464U-Z 制造商:Cirrus Logic 功能描述:EVAL BD PB-FREE DEMO BOARD FOR CS5464 - Boxed Product (Development Kits) 制造商:Cirrus Logic 功能描述:Eval Board
CDB5466U 功能描述:数据转换 IC 开发工具 Eval Bd F/Residental Pow-Meter Apps RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V
CDB5466U-Z 制造商:Cirrus Logic 功能描述:PB-FREEEVAL BOARD FOR CS5466 WITH USB - Bulk